1. Field of the Invention
The present invention relates to a method and a circuit for driving a liquid crystal panel, and in particular to a method and a circuit for driving an active matrix liquid crystal panel.
2. Description of the Related Art
A conventional digital driver for driving a liquid crystal panel will be described.
FIG. 1A is a block diagram showing a part of a conventional 3-bit digital driver corresponding to one output. Such a part corresponds to each of a plurality of data lines provided in a liquid crystal panel and will be referred to as a "driving unit", which is represented by reference numeral 102a in FIG. 1A. The 3-bit digital driver includes the number of driving units corresponding to the number of data lines provided in the liquid crystal panel.
As shown in FIG. 1A, the driving unit 102a includes a sampling memory (MSMP) 10 for sampling 3-bit digital image data at the rise of a sampling pulse TSMP, and a holding memory (MH) 20 for holding the digital image data sampled by the sampling memory 10 at the rise of an output pulse LS which is in phase of a horizontal synchronization (Hsyn) signal. The driving unit 102a further includes an output circuit (OPC) 30 for converting the digital image data held by the holding memory 20 into a voltage corresponding to the value of the digital image data and outputting the resultant voltage. The output circuit 30 receives eight types of gray scale voltages V0 through V7 from an external device.
The driving unit 102a operates in the following manner.
Digital image data is sampled by the sampling memory 10 at the rise of a sampling pulse TSMP, and is then held by the holding memory 20 at the rise of an output pulse LS. The digital image data held by the holding memory 20 is converted into a voltage corresponding to the value of the digital image data and is output by the output circuit 30. In other words, the output circuit 30 selects one of the gray scale voltages V0 through V7 corresponding to the value of the digital image data and outputs the selected voltage to a data line DLn corresponding to the driving unit 102a. The output pulse LS is output after the sampling of digital image data is finished in the driving units corresponding to all the data lines provided in the liquid crystal panel.
FIG. 1B is a circuit diagram of the output circuit 30. As shown in FIG. 1B, the output circuit 30 includes a decoder (DEC) 31 for converting the 3-bit digital image data into eight switching control signals S0 through S7, and a switch group 32 including eight analog switches ASW0 through ASW7 respectively for receiving the eight switching control signals from the decoder 31 and outputting the corresponding gray scale voltages V0 through V7 to the data line DLn.
The output circuit 30 operates in the following manner.
When a switching control signal corresponding to the value of the digital image data held by the holding memory 20 turns on an analog switch corresponding to the switching control signal, the gray scale voltage received by the analog switch is output from the output circuit 30.
When the value of the data is "4", for example, only the switching control signal S4 is activated among the eight switching control signals in the decoder 31. The switching control signal S4 turns ON the analog switch ASW4. Accordingly, the gray scale voltage V4 received by the analog switch ASW4 is output to the data line DLn.
FIG. 2 is a timing diagram illustrating the waveforms of AC signals used for driving a liquid crystal panel by the driving unit 102a. Specifically, FIG. 2 shows the waveforms of the gray scale signals, the Hsyn signal, a polarization (POL) signal, and a latch strobe (LS) signal. The LS signal includes a series of pulses which are output in phase with the Hsyn signal. In phase with the LS signal, the digital image data sampled by the sampling memory 10 is held by the holding memory 20 and output to the output circuit 30. The polarity (POL) signal indicates whether the voltage to be applied to the pixel electrode should be higher or lower than the voltage Vcom of the common electrode by the unit of a time period. The voltage to be applied to the common electrode will be referred to as "common electrode voltage Vcom". The time period in which the voltage to be applied to the pixel electrode should be higher (positive) with respect to the common electrode voltage Vcom is referred to as a "positive driving period", and the time period in which the voltage to be applied to the pixel electrode should be lower (negative) with respect to the common electrode voltage Vcom is referred to as a "negative driving period". The common electrode voltage Vcom is inverted with a center voltage Vcent as the center in phase with the POL signal.
In FIG. 2, only the gray scale voltages V0, V3, V4 and V7 are shown, the other gray scale voltages V1, V2, V5 and V6 being omitted for simplicity. The gray scale voltage V0 corresponds to gray scale data 0 and has the largest difference from the common electrode voltage Vcom. The gray scale voltage V7 corresponds to gray scale data 7 and has the smallest difference from the common electrode voltage Vcom. The gray scale voltages V3 and V4 are median between the gray scale voltages V0 and V7. Symbols v0, v3, v4 and v7 represent potentials of the gray scale voltages V0, V3, V4 and V7 in the positive driving period, and -v0, -v3, -v4 and -v7 represent potentials of the gray scale voltages V0, V3, V4 and V7 in the negative driving period.
The waveforms shown in FIG. 2 are used in a line inversion driving method, by which the polarity of the voltage to be applied changes line by line (gate line by gate line). The waveform of each gray scale voltage is determined so that the polarity of the voltage changes frame by frame (i.e., vertical period by vertical period). In other words, the waveforms of the gray scale voltages are inverted in phase of both the Hsyn signal and the vertical horizontal (Vsyn) signal.
This can be appreciated from FIG. 3, which shows the waveforms of the gray scale V0 in two frames together with the Vsyn and Hsyn signal. The polarity of the gray scale signal V0 is inverted horizontal period by horizontal period, and the polarities in a first frame are opposite to those in the next frame.
By the conventional driving method, as shown in FIG. 2, the output timing of the LS signal and the inverting point of the POL signal are substantially the same. This is inevitable because output of data starts by the output pulse LS. Due to such a manner of operation, the ratio of the time period in which a desired voltage is output from the driver with respect to the positive and negative driving period can be maximized.
FIG. 4 is a timing diagram illustrating waveforms for writing image data "0" and "4" to one data line together with the Vsyn signal and the Hsyn signal. Waveform W0 represents the voltage for writing image data "0" to pixels connected to one data line, and waveform W04 represents the voltage for alternately writing image data "0" and "4" to pixels connected to one data line.
Chain line Va represents an average voltage of the waveform W0 in one frame. When only display data "0" is written, the average voltage Va is equal in each two adjacent frames.
When image data "0" and "4" are alternately written, the average voltage of the waveform W04 has an average voltage Va1 in a first frame and another average voltage Va2 in a second frame which follows the first frame. As shown in FIG. 4, the average voltage Va1 is different from the average voltage Va by .DELTA.Va(+) in the positive direction, and the average voltage Va2 is different from the average voltage Va by .DELTA.Va(-) in the negative direction. As can be seen from these waveforms, when different display data, for example V0 and V4, are written in pixels connected to one data line, the average voltage of the waveform changes frame by frame between a value higher than the average voltage Va of waveform W0 by a certain level and another value lower than the average voltage Va by the same level.
FIG. 5A is an equivalent circuit diagram generally used in a liquid crystal panel. Such an equivalent circuit diagram is disclosed in, for example, Y. Kanamori et al., "10.4-inch. Diagonal Color TFT-LCDs without Residual Images SID'90", pp. 408-411 (1990). A pixel capacitance CLc is determined by a pixel electrode, a common electrode and a dielectric liquid crystal material interposed between the pixel electrode and the common electrode. The potential difference between the pixel electrode and the common electrode is applied to the liquid crystal material. A floating capacitance Cgd is generated by the gate electrode and the drain electrode of the TFT used as a switching device. A storage capacitor Cs can be formed in various structures. In this example, the storage capacitor Cs is formed between the pixel electrode and a gate line which is previous to the gate line to which the pixel electrode is connected.
When a liquid crystal panel is driven by the equivalent circuit shown in FIG. 5A while AC-driving the common electrode, it is preferable to minimize the change in charge level in the pixel capacitance CLc in order to obtain an image having a satisfactory quality. This is because the voltage applied to the liquid crystal material held between the pixel electrode and the common electrode is determined by the level of charge in the pixel capacitance CLc.
One method proposed to minimize the change is a floating gate method, by which the off-state voltage from the gate driver has the same waveform as that of the voltage applied to the common electrode except for the DC component. The floating gate method is disclosed in, for example, Okada et al., "8.4-inch. Color TFT Liquid Crystal Display and its Driving Technology", Technical Report of the Institute of Electronics, Information and Communication Engineers, Vol. 92, No. 467, pp. 27-33 (1993).
In the display apparatus described in the above-mentioned publication, the gate driver outputs voltages to the gate line which are DC voltages with respect to the common electrode voltage. Since the capacitances in FIG. 5B vary significantly in accordance with the structure of the TFT, satisfactory display can be obtained in different ways when certain types of display mediums are used. Even if the display quality is deteriorated by the floating method to a certain extent, a problem may not occur depending on the use of the display apparatus, or alternatively, other methods can be used for the same purpose. The floating method is one solution for driving the liquid crystal panel using the equivalent circuit shown in FIG. 5A, but is not the only solution. This is described in the above publication.
In the equivalent circuit shown in FIG. 5A, elements which may influence the display quality, namely, elements which may change the charge in the pixel capacitance CLc on the side of the TFT, are potentials of the electrodes opposed to the pixel electrodes with capacitances CLc, Cs, and Cgd interposed therebetween. That is, the elements which may influence the display quality are the common electrode and the gate lines. As can be appreciated from this, the potential of the data line is conventionally considered not to influence the display quality.
Accordingly, in the case of an ideal off-period of the TFT, even when the average potential of the data line changes frame by frame as shown in FIG. 4, such a change does not influence the display quality.
As described above, it is conventionally considered that the potential of the data line does not influence the potential of the pixel electrode after the TFT is turned off. In other words, the off-state resistance of the TFT is considered to be infinite and the capacitances are considered to be zero. This is an ideal state, which is not realized in TFTs used today, and accordingly the off-state resistance and the capacitances do influence the potential of the pixel electrode. The degree of influence varies in accordance with, for example, the material and structure of the TFT. When the degree of influence is excessive, the driving timing and driving waveforms which are determined based on the equivalent circuit shown in FIG. 5A needs to be corrected.
FIG. 5B is an equivalent circuit of the pixel including the off-state resistance Roff and the source-drain capacitance Csd of the TFT. As appreciated from FIG. 5B, the potential of the data line influences the charge of the pixel capacitance CLc on the side of the TFT through the off-state resistance Roff and the source-drain capacitance Csd. The minimum level of the off-state resistance Roff and the source-drain capacitance Csd which deteriorates the display quality depends on various elements. The reason is the intolerable degree of deterioration depends on the liquid crystal material, the number of gray scales which can be displayed, the image pattern, and also the use of the display apparatus.
With reference to FIGS. 6A and 6B, the problem of the conventional driving method caused by the source-drain capacitance Csd of the TFT will be described.
FIG. 6A shows a screen displaying an image pattern conspicuously showing the above-described problems. The image pattern has areas A through E. Central area E has an entirely uniform luminance corresponding to image data "4". In areas A through D, a checkered pattern appears by the different levels of luminance in correspondence with the image data "0" and "4" as shown in FIG. 6B.
When such a checkered pattern appears, the luminance of areas C and D sandwiching central area E change entirely. This occurs because the different average potentials of the data line inside and outside area E influence the potential of the pixel electrodes to different degrees.
FIG. 7 is a timing diagram showing the average potential of one data line, the charging potentials of pixels X and Y connected to the data line in areas C, E and D for two frames. Pixel X is in area C, and pixel Y is in area D. Pixel X is influenced by the potential of the data line in the frame in which pixel X is charged, but pixel Y is influenced by the potential of the data line in the frame following the frame in which the pixel Y is charged. Thus, the direction of change of potentials of pixel X is opposite to that for pixel Y. In this manner, the luminance of areas C and D sandwiching area E entirely change.